Post on 19-Mar-2020
transcript
Lab. de Diseño de Circuitos y Sistemas Electrónicos. 4º Ing. Electrónica
Profesores: Alfredo Rosado. Manuel Bataller. 1
Práctica 6. Implementación de descripciones VHDL en dispositivos Xilinx 1. Introducción.
En esta sesión de laboratorio se pretende realizar un diseño VHDL capaz de ser sintetizado sobre un
dispositivo físico de Xilinx. El único problema que esto plantea es que además de disponer de un código VHDL correcto, éste debe ser sintetizable y adaptarse a las normas de síntesis para Xilinx, con lo que la obtención de un código VHDL correcto hasta poder realizar la simulación puede ser más laboriosa.
Por otra parte, será necesario realizar una correcta asignación de restricciones en la implementación sobre dispositivo para permitir que las entradas y salidas definidas correspondan con las patillas existentes en el dispositivo cableadas a sus correspondientes elementos de entrada/salida.
2. Objetivo de la práctica.
Diseñar en VHDL e implementar sobre FPGA, un cronómetro digital que muestre décimas de segundo, segundos, y minutos.
Esta implementación se realiza sobre el dispositivo Virtex-E XCV100E-6C PQ240. Las décimas de segundo se muestran en los LED que la placa de pruebas posee (la misma placa ya
empleada en la práctica primera de Xilinx), de tal modo que se enciende un LED diferente por cada décima de segundo que pasa, realizando un efecto de desplazamiento del LED iluminado. Nombre : decimas_led<9>..decimas_led<0>. NOTA: Sólo existen 8 LED, con lo que los otros dos restantes se asignarán a los puntos decimales de los display de 7 degmentos.
Los segundos se muestran en los dos display de 7 segmentos que están conectados a la placa (Nombre : seg7seg1<6>..seg7seg1<0> y seg7seg2<6>..seg7seg2<0>). En cuanto a los minutos, éstos se muestran como 14 salidas no conectadas a nada y que en principio no se puede acceder con los recursos de visualización que la placa proporciona, pero que debemos ser capaces de simular (Nombre : seg7min1<6>..seg7min1<0> y seg7min2<6>..seg7min2<0>).
Se dispone de dos botones tipo pulsador, uno de inicio/paro de cuenta (Nombre : ini_paro), y otro de reset de cuenta (Nombre : clear). Suponemos que tenemos un reloj externo de frecuencia 10Hz (Nombre : clock. Existe una salida de fin de cuenta (Nombre: TC) que indica si el contador de minutos ha llegado al final. La representación de la salida sería:
MINUTOS SEGUNDOS décimas 2.1. Pasos a seguir.
El diseño es altamente modular, con lo que se puede hacer uso de un mismo módulo en varias ocasiones.
Los pasos a seguir son los siguientes: 1. Especificar el funcionamiento del diseño. Plantear la concepción global del sistema y posteriormente
desarrollar cada parte del mismo. 2. Describir los diversos módulos en VHDL. Recordar que las salidas a display 7 segmentos y a LED
son activas a nivel alto. 3. Unir todos los módulos para conformar el sistema completo. 4. Generar un banco de pruebas y simular el diseño en ModelSim. Puede resultar aconsejable simular
por separado cada módulo antes de simular el diseño completo.
Lab. de Diseño de Circuitos y Sistemas Electrónicos. 4º Ing. Electrónica
Profesores: Alfredo Rosado. Manuel Bataller. 2
5. Una vez que el diseño es correcto en simulación, asignar el patillaje de las entradas y salidas empleadas por el diseño. Servirse de las hojas de datos de la placa (Data Sheet) para conocer la correspondencia de cada patilla con la entrada/salida correspondiente. Como única indicación, tened en cuenta que de las diversas patillas de reloj, se debe usar OSC (patilla 92).
6. Sintetizar el diseño y comprobar que no hay errores de síntesis, si los hubiera, probablemente sería necesario modificar el código VHDL para que éste sea sintetizable.
7. Implementar en el dispositivo XCV100E-6C PQ240. 8. Si la implementación se realiza con éxito, descargar el programa en la placa de pruebas (la misma
placa que en la primera práctica de Xilinx) y chequear el correcto funcionamiento conectando un generador de señal cuadrada de 10Hz de frecuencia a la entrada de reloj.
3. Consideraciones en la implementación.
Puede ocurrir que en el proceso de implementación, además de la señal clock, alguna otra señal sea
detectada como señal de reloj; ello fuerza a que esta señal sea asignada obligatoriamente en una de las patillas especialmente dedicadas para el reloj. Por el contrario, en la placa disponible sólo es accesible como patilla de reloj la patilla 92, por lo que si esto ocurre será necesario forzar a la implementación para que no asigne la/las señal/es a patillas de reloj. Esto se consigue con la inclusión de la siguiente instrucción dentro del código VHDL:
attribute clock_buffer: string; attribute clock_buffer of <nombre_señal_entrada> : signal is “ibuf”;
donde <nombre_señal_entrada> es el nombre de la señal de entrada declarada en la entidad que queremos evitar que sea asignada a una patilla específica de reloj.
4. Documentación a entregar.
En las dos semanas siguientes a la realización de la práctica, se entregará un pequeño dossier que incluya la descripción del proceso de diseño, el código VHDL del diseño propuesto, los resultados de la simulación, y los resultados de la implementación (lógica necesaria ? CLB ocupados, velocidad máxima de funcionamiento, y aquellos datos que se consideren relevantes en el diseño), así como la opinión personal acerca de la práctica realizada y dificultades encontradas en el desarrollo de la misma.
Xilinx® Virtex™ -E Evaluation Kit
November 28, 2000 (Version 1.1) DRAFT Advance Product Specification
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 1©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.All other trademarks and registered trademarks are the property of their respective owners.
Features• FPGA
� Xilinx® Virtex-E XCV100E-6PQ240C• SPROM
� Xilinx® XC18V01SO20C• Board I/O Connectors
� Two 50-pin, 0.1 Header connector� Pads for three MICTOR connectors� Pads for one 140 pin General Purpose I/O
interface• Power
� +5.0 Power Connector� +3.3 V Regulated Supply� +1.8 V Regulated Supply� Full Bypass Capacitance
• Communication� RS232 Serial Port
• Configuration� JTAG Header Connector� In-System Programmable PROM� JTAG Download Cable
• Miscellaneous� 8 DIP switches� 2 Push-buttons,� Dual Digit 7 Segment LED, right hand decimal� Infrared Transceiver� 8 LEDs� 40 MHz Oscillator� Digital Thermometer
• Demonstration application (Source VHDL)� Simple RS232� Digital Thermometer� LED Patterns
DescriptionThe Evaluation Virtex-E Kit is used by engineers as aplatform to test FPGA designs that are targeted to theXilinx Virtex-E device. It is also a great tool for beginnersto get aquatinted with FPGAs and VHDL.
The Virtex-E device is located in the center of the board. Itcan be configured via a JTAG download or from the onboard configuration PROM. The configuration PROM isalso programmable through the JTAG cable. Over 85 IOsignals are connected from the FPGA to 0.1 headerconnectors for user connections. Other IO are connectedto 8 LED, 8 dip switches, Two push buttons, RS-232 linedriver/receiver, and a digital thermometer.
Demo Application.The board is supplied with complete VHDL source codethat:
1) Sequences LEDs2) Reads Dip Switches/push buttons3) Senses Temperature and displays value on
dual 7 segment LED4) Transmits startup message through RS-232
connector.5) Echoes RS-232 commands. (Serial cable not
included)
Ordering InformationThe following table lists the development system partnumbers and available software options.Internet Link at http://www.em.avnet.com/.
Table 1 Evaluation Virtex-E Board
Part Number HardwareADS-XLX-VE-EVL Xilinx Virtex-E Evaluation Kit
Xilinx Virtex-E Evaluation Kit
Page - 2 Literature # ADS-001205 November 28, 2000 (Version 1.1)©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
ADS Evaluation Virtex-E BoardThis section provides information basic to the design ofEvaluation Virtex-E Board board.
PowerThe majority of the design is powered at 3.3V with theVirtex-E FPGA core powered at 1.8V. The board shouldbe powered by a 5-volt bench supply. The 3.3V is derivedvia a linear regulator. A linear regulator from the 3.3Vprovides the 1.8V Xilinx core voltage. A barrel connectorJ3 (RAPC712) is provided on the board for lab supplyconnections. The center tap is +5.0 volts and the outer isGND. Note: The lab supply should be regulated at 5.0volts. While current requirements are dependent on theuser application, it is suggested to limit your supply to 1.5amps on initial power up.
φ 0.098 inpin diameter
φ 0.25 inhousing diameter
+5.0 Volts GND
Printed Circuit BoardThe Evaluation Virtex-E Board printed circuit board is an6-layer board with four signal layers, a full 3.3V powerplane incorporating an isolated 1.8V mini-plane, and fullground plane. The board stack-up layers 1 through 6 is:
1) ”Component side”/signal2) Ground Plane3) Signal4) Signal5) Power: 3.3V and 1.8V6) ”Solder side”/signal
Virtex-E FPGAThe Virtex-E Field-Programmable Gate Array device (U1)utilized in this design is the 100+K-system gate device(XCV100E) in a PQ240 package.
FPGA ConfigurationConfiguration information is provided from two sources;the JTAG Connector (JTAG0), and configuration PROM.
Table 2 JTAG Connector
Signal Name JTAG Connector Pin #VCC 1TDI 2TMS 3TCK 4TDO 5GND 6
Jumpers JP1, JP2 and JP3 select the configuration mode ofthe Virtex. The following table shows the jumper settingneeded for each mode.
Table 3 Mode Select
ConfigurationMode
Pull-ups
JP3/M2 JP2/M1 JP1/M0
Master-serial No OFF /LOW OFF /LOW OFF /LOWBoundary-scan No ON /HIGH OFF /LOW ON /HIGH
SelectMAP No ON /HIGH ON /HIGH OFF /LOWSlave-serial No ON /HIGH ON /HIGH ON /HIGH
Master-serial Yes ON /HIGH OFF /LOW OFF /LOWBoundary-scan Yes OFF /LOW OFF /LOW ON /HIGH
SelectMAP Yes OFF /LOW ON /HIGH OFF /LOWSlave-serial Yes OFF /LOW ON /HIGH ON /HIGH
The LED D1 indicates the output level of the DONE pin ofthe Virtex-E device. It will illuminate when the Virtex-Econfiguration is complete.
System ClockAn oscillator socket clock output is connected to theVirtex-E device. U5 is connected to Global Clock Input #0(PQ240 pin #P92), The U5 socket is populated with a 40MHz oscillator.
Asynchronous (RS232) CommunicationInterfaceThe ADM3222 device provides level translation for asingle RS232 interface (DB9 connector). The secondtranslation port on the device is terminated and unused.
Xilinx Virtex-E Evaluation Kit
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 3©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.All other trademarks and registered trademarks are the property of their respective owners.
Table 4 RS232 Interface Signals
RS232 SIGNAL Virtex-E PIN #R1OUT P216
T1IN P217EN_N P218SD_N P219
Table 5 RS232 Connector Pinout
Signal Name P2 (DB9) connector Pin #TX out 2RX in 3GND 5
MiscellaneousThe “Miscellaneous” interfaces on the Virtex-E boardconsist of a single 8-position DIP switch (8-individualSPST switches), 8 LEDs, and two push-button switches.
Table 6 Dip Switch Signals
DIP SW Virtex-E PIN ##1 P194#2 P195#3 P199#4 P200#5 P201#6 P202#7 P203#8 P205
Table 7 Push Button Switch Signals
BUTTON Virtex-E PIN #SW1 P206SW2 P208
Table 8 LED Control Signals
LED Virtex-E PIN #
D2 P27D3 P28D4 P3D5 P4D6 P5D7 P6D8 P7D9 P9
Table 9 Dual Segmented LED Signals
LED Virtex-E PIN #
A1 P221B1 P222C1 P223D1 P224E1 P228F1 P229G1 P230
Dp1 P231A2 P234B2 P235C2 P236D2 P237E2 P238F2 P186G2 P187
Dp2 P188
Table 10 Infrared Signals
LED Virtex-E PIN #
TXD P102RXD P101
SHDN P100
Table 11 Digital Themometer
LED Virtex-E PIN #
CE P160SCLK P159SDI P161SDO P162
Xilinx Virtex-E Evaluation Kit
Page - 4 Literature # ADS-001205 November 28, 2000 (Version 1.1)©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
I/O Signal HeadersTwo 50-pin connectors provides 84 Virtex-E I/O lines and6 ground pins.
Table 12 GPIO Signals JP5
GPIO CONNECTOR PIN#
Virtex-E PIN #
1 P862 P843 P824 P815 P806 P797 P788 P749 P7310 P7211 P7112 P7013 P6814 P6715 P6616 P6517 P6418 P6319 P9920 P9721 P9622 P9523 P9424 P11825 P11726 P11527 P11428 P11329 P11130 P11031 P10932 P10833 P14934 P14735 P14436 P14237 P14138 P14039 P13440 P13341 P13242 P13143 P13044 Reserved45 Reserved46 Reserved47 Reserved48 GND49 GND50 GND
Table 13 GPIO Signals JP6
GPIO CONNECTOR PIN#
Virtex-E PIN #
1 P312 P333 P344 P355 P366 P387 P398 P409 P4110 P4211 P4612 P4713 P4814 P4915 P5016 P5217 P5318 P5419 P5620 P5721 P1022 P1123 P1224 P1325 P1726 P1827 P1928 P2029 P2130 P2331 P2432 P2633 P12834 P12735 P12636 P12537 P17538 P17439 P17340 P17141 P17042 P16943 Reserved44 Reserved45 Reserved46 Reserved47 Reserved48 GND49 GND50 GND
Xilinx Virtex-E Evaluation Kit
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 5©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.All other trademarks and registered trademarks are the property of their respective owners.
Logic Analyzer ConnectorThree AMP™ MICTOR connector pads are provided toconnect to a logic analyzer’s mass termination cable.
Table 14 MICTOR J4
Connector PIN # Virtex-EPIN #
Name
1 N/C N/C2 N/C N/C3 N/C N/C4 N/C N/C5 P210* CLK_OUT6 P92 OSC7 P108 ADDRESS318 P65 ADDRESS159 P109 ADDRESS3010 P66 ADDRESS1411 P110 ADDRESS2912 P67 ADDRESS1313 P111 ADDRESS2814 P68 ADDRESS1215 P113 ADDRESS2716 P70 ADDRESS1117 P114 ADDRESS2618 P71 ADDRESS1019 P115 ADDRESS2520 P72 ADDRESS921 P117 ADDRESS2422 P73 ADDRESS823 P118 ADDRESS2324 P74 ADDRESS725 P94 ADDRESS2226 P78 ADDRESS627 P95 ADDRESS2128 P79 ADDRESS529 P96 ADDRESS2030 P80 ADDRESS431 P97 ADDRESS1932 P81 ADDRESS333 P99 ADDRESS1834 P82 ADDRESS235 P63 ADDRESS1736 P84 ADDRESS137 P64 ADDRESS1638 P86 ADDRESS039 GND GND40 GND GND41 GND GND42 GND GND43 GND GND
Table 15 MICTOR J5
Connector PIN # Virtex-EPIN #
Name
1 N/C N/C2 N/C N/C3 N/C N/C4 N/C N/C5 P213* GCK36 P89* GCLK17 P26 DATA318 P52 DATA159 P24 DATA30
10 P50 DATA1411 P23 DATA2912 P49 DATA1313 P21 DATA2814 P48 DATA1215 P20 DATA2716 P47 DATA1117 P19 DATA2618 P46 DATA1019 P18 DATA2520 P42 DATA921 P17 DATA2422 P41 DATA823 P13 DATA2324 P40 DATA725 P12 DATA2226 P39 DATA627 P11 DATA2128 P38 DATA529 P10 DATA2030 P36 DATA431 P57 DATA1932 P35 DATA333 P56 DATA1834 P34 DATA235 P54 DATA1736 P33 DATA137 P53 DATA1638 P31 DATA039 GND GND40 GND GND41 GND GND42 GND GND43 GND GND
Xilinx Virtex-E Evaluation Kit
Page - 6 Literature # ADS-001205 November 28, 2000 (Version 1.1)©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Table 16 MICTOR J6
Connector PIN # Virtex-EPIN #
Name
1 N/C N/C2 N/C N/C3 N/C N/C4 N/C N/C5 P210* CLK_OUT6 P191* CLK_IN7 P178 DOUT8 P175 CNTL159 P208 SWITCH9
10 P125 CNTL1411 P206 SWITCH812 P126 CNTL1313 P162 TEMP_SDO14 P127 CNTL1215 P161 TEMP_SDI16 P128 CNTL1117 P160 TEMP_CE18 P130 CNTL1019 P159 TEMP_SCLK20 P131 CNTL921 P220 RS232SD_N22 P132 CNTL823 P218 RS232EN_N24 P133 CNTL725 P217 RS232TX26 P139 CNTL627 P216 RS232RX28 P140 CNTL529 P169 CNTL2030 P141 CNTL431 P170 CNTL1932 P142 CNTL333 P171 CNTL1834 P144 CNTL235 P173 CNTL1736 P147 CNTL137 P174 CNTL1638 P149 CNTL039 GND GND40 GND GND41 GND GND42 GND GND43 GND GND
*Note: A zero ohm resistor may be required to access thenoted signals.
AvBus ConnectorHigh-density connector pads are located on bottom of theboard. The signals are listed in the following table.
Table 17 AvBus Connector P2
Name FPGAPIN #
Connector PIN # FPGAPIN #
Name
ADDRESS0 P86 71 1 N/C N/CGND GND 72 2 P84 ADDRESS1
ADDRESS3 P81 73 3 P82 ADDRESS3ADDRESS4 P80 74 4 GND GND
GND GND 75 5 P79 ADDRESS5ADDRESS7 P74 76 6 P78 ADDRESS6ADDRESS8 P73 77 7 GND GNDAUX_+3.3V +3.3V 78 8 P72 ADDRESS9ADDRESS11 P70 79 9 P71 ADDRESS10ADDRESS12 P68 80 10 GND GND
GND GND 81 11 P67 ADDRESS13ADDRESS15 P65 82 12 P66 ADDRESS14ADDRESS16 P64 83 13 N/C N/C
GND GND 84 14 P63 ADDRESS17ADDRESS19 P97 85 15 P99 ADDRESS18ADDRESS20 P96 86 16 GND GND
GND GND 87 17 P95 ADDRESS21ADDRESS23 P118 88 18 P94 ADDRESS22ADDRESS24 P117 89 19 GND GNDAUX_+3.3V +3.3V 90 20 P115 ADDRESS25ADDRESS27 P113 91 21 P114 ADDRESS26ADDRESS28 P111 92 22 GND GND
GND GND 93 23 P110 ADDRESS29ADDRESS31 P108 94 24 P109 ADDRESS30
DATA0 P31 95 25 N/C N/CGND GND 96 26 P33 DATA1
DATA3 P35 97 27 P34 DATA2DATA4 P36 98 28 GND GND
GND GND 99 29 P38 DATA5DATA7 P40 100 30 P39 DATA6DATA8 P41 101 31 GND GND
AUX_+3.3V +3.3V 102 32 P42 DATA9DATA11 P47 103 33 P46 DATA10DATA12 P48 104 34 GND GND
GND GND 105 35 P49 DATA13DATA15 P52 106 36 P50 DATA14DATA16 P53 107 37 N/C N/C
GND GND 108 38 P54 DATA17DATA19 P57 109 39 P56 DATA18DATA20 P10 110 40 GND GND
GND GND 111 41 P11 DATA21DATA23 P13 112 42 P12 DATA22DATA24 P17 113 43 GND GND
AUX_+3.3V +3.3V 114 44 P18 DATA25DATA27 P20 115 45 P19 DATA26DATA28 P21 116 46 GND GND
GND GND 117 47 P23 DATA29DATA31 P26 118 48 P24 DATA30CNTL0 P149 119 49 N/C N/CGND GND 120 50 P147 CNTL1
CNTL3 P142 121 51 P144 CNTL2CNTL4 P141 122 52 GND GNDGND GND 123 53 P140 CNTL5
CNTL7 P133 124 54 P139 CNTL6CNTL8 P132 125 55 GND GND
AUX_+3.3V +3.3V 126 56 P131 CNTL9CNTL11 P128 127 57 P130 CNTL10
Xilinx Virtex-E Evaluation Kit
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 7©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.All other trademarks and registered trademarks are the property of their respective owners.
Name FPGAPIN #
Connector PIN # FPGAPIN #
Name
CNTL12 P127 128 58 GND GNDGND GND 129 59 P126 CNTL13
CNTL15 P175 130 60 P125 CNTL14CNTL16 P174 131 61 N/C N/C
GND GND 132 62 P173 CNTL17CNTL19 P170 133 63 P171 CNTL18CNTL20 P169 134 64 GND GND
GND GND 135 65 P191* CLK_INCLK_OUT P210* 136 66 P210* CLK_OUT_FB
TMS ⊕ 137 67 GND GNDAUX_+3.3V +3.3V 138 68 ⊕ TDO
TDI ⊕ 139 69 ⊕ TCKTRS ⊕ 140 70 GND GND
*Note: A zero ohm resistor may be required to access thenoted signals.⊕Note: Reference Schematic for current JTAG signalpaths.
Demonstration ProgramSupplied with the development system is a demonstrationprogram file that utilizes several devices on the evaluationboard. The demonstration program uses the evaluationdevelopment board as a standalone platform that isconnected to a lab supply and a terminal emulationprogram. On power up the onboard PROM will configurethe FPGA. Upon completion of the configuration theFPGA functionality and input/output signal will activate.A start up serial message will be sent to the terminal portvia the RS-232 connection. The LEDs will display a backand forth scanning pattern or 8-bit value corresponding tothe current temperature. The Dual segmented display willcount up or display the current temperature.
Additional Items Needed:� Lab power supply, 5.0 volts at 1.5 amps.� Serial Terminal or Terminal Emulator.� RS-232 cable
Setup:1) Attach the lab supply to the power connector on
the Evaluation Board.2) Attach the serial terminal to the P1 connector of
the Evaluation Board.3) Set the Serial Terminal to: 8 data bits, 1 stop , No
parity, 9600 baud.4) Verify jumper are NOT installed on JP1,JP2,and
JP3.5) Verify JP4 is installed across pins 1 and 2.
Power UP:6) Apply power to the Evaluation Board.7) The DONE LED D1 will light on the completion
of the download.Reset:
8) Press the Soft Reset button SW1 to reset theboard.
Serial Demo9) Press the button SW2 to send the startup message.10) The Power up message is displayed on the serial
terminal.11) All characters typed should be echoed to the
terminal.12) Press the Reset button again to “reset” startup
message.LED SCAN
13) Set the dipswitch S1 dip 1 to ON (rocker up).14) The LEDs should be blinking such that the
illuminated led should be scanning back and forththrough the LED array.
UP COUNTER15) Set the dipswitch S1 dip 2 to ON (rocker down).16) The Dual segmented LEDs should be counting
up.TEMPERATURE
17) Set the dipswitch S1 dip 1 to OFF (rocker down).18) The LED should now display the temperature in
°C in two’s complement binary. See the followingtable.
19) Set the dipswitch S1 dip 2 to OFF (rocker down).20) The Dual segmented LEDs should now display
the temperature in °C.21) Hold your finger on U5 to change the
temperature.
LED Pattern(D9..D2)
Decimal Value (°C)
0111 1000 +120C0001 1001 +25C0000 1010 +10C0000 0000 0C1111 0101 -10C1110 0110 -25C1100 1001 -55C
Xilinx Virtex-E Evaluation Kit
Page - 8 Literature # ADS-001205 November 28, 2000 (Version 1.1)©2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Relevant DocumentsDocuments relevant to this application are listed in thefollowing table.
Table 18. Relevant Documents and Links
Document SourceXILINX VIRTEX-E FPGA DataSheet
http://www.xilinx.com/partinfo/ds022.pdf
Document SourceXILINX XC18V01 ConfigurationPROM Data Sheet
http://www.xilinx.com/partinfo/ds026.pdf
Analog Devices ADM3222 3VRS232 Line Driver/Receiver DataSheet
http://www.analog.com/pdf/ADM3202_0.pdf
Block Diagram
RevisionsVersion 1.0 Initial Release.Version 1.1 Fixed typographical errors.
50 P
inH
eade
r
XILINXXC18V01SO20C
ConfigurationPROM
8 LE
DS
DigitalThermometer
40MHzOSC A
vBus
Boa
rd to
Boa
rd14
0 P
in C
onne
ctor
RS-232
JTAG Header
3 MICTORs
50 P
inH
eade
r
8 D
ip S
witc
hes
2 PushButtons
XILINXVIRTEX-E
XCV100E-6PQ240
FPGA
Dual8-Segment
LED
InfraredTransceiver
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4
Copyright 2000, Avnet, Inc. All Rights Reserved.
This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied inany form or by any means without the prior written permission of Avnet, Inc. AVNET and the AV logo areregistered trademarks of Avnet, Inc. All trademarks and trade names are the properties of their respectiveowners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and tradenames other than its own.
Avnet is not responsible for typographical or other errors or omissions or for direct, indirect, incidental orconsequential damages related to this material or resulting from its use. Avnet makes no warranty orrepresentation respecting this material, which is provided on an "AS IS" basis. AVNET HEREBYDISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING,WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALLIMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR FITNESS FOR APARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not designed, intendedor authorized for use in medical, life support, life sustaining or nuclear applications or applications in whichthe failure of the product could result in personal injury, death or property damage. Any party using orselling products for use in any such applications do so at their sole risk and agree that Avnet is not liable,in whole or in part, for any claim or damage arising from such use, and agree to fully indemnify, defend andhold harmless Avnet from and against any and all claims, damages, loss, cost, expense or liability arisingout of or in connection with the use or performance of products in such applications.
Mictor and Header Connectors
2
Mini-Virtex-E Evauation Board
Sheet Number
Power
Function
FPGA, SPROM
www.em.avnet.com
3
1
Avnet Design Services
Switch, LED, OSC 5
Lead Sheet
Initial Release
REV SHEET DATE
A
DESCRIPTION
ALL 11-OCT-2000
6Daughter Board Connector
LIT# ADS-001207
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Lead Sheet
B
1Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOT POPULATEDNOT POPULATED
NOT POPULATED
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Lead Sheet
C
2Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
MODE0
TMS
FPGA_TDOTCK
CCLKINIT_N
TMSTCK
D0
DONE
SP_TDI
CONN_TDO
CONN_TDI
TMS
TCK
FP
GA
_TD
O
SP
_TD
I
CO
NN
_TD
O
FP
GA
_TD
O
CO
NN
_TD
I
SP
_TD
I
MODE2
SP_TDO
CS_N
CONN_TCK
CONN_TCK
CONN_TMS
CONN_TMS
DA
TA
30
DA
TA
1
TC
K
FP
GA
_TD
O
DA
TA
10
DA
TA
3
DO
NE
DA
TA
19
DA
TA
15
DA
TA
2
WRITE_NCS_N
MO
DE
2
INIT
_N
D0
SP
_TD
O
MO
DE
0
DA
TA
28
DA
TA
21
DA
TA
17
DA
TA
8
DA
TA
13D
AT
A12
MO
DE
1
DA
TA
24
ADDRESS23
CC
LK
CF
_N
DA
TA
23
DA
TA
29
DA
TA
20
DA
TA
0
TM
S
DA
TA
25
DA
TA
18
DA
TA
26
DA
TA
16
DA
TA
14
DA
TA
31
DA
TA
4
DA
TA
11
DA
TA
9
DA
TA
5
MODE1
DA
TA
27
DA
TA
7
WRITE_N
DA
TA
22
DA
TA
6
ADDRESS24
ADDRESS29ADDRESS28
ADDRESS31
ADDRESS25ADDRESS26
ADDRESS30
ADDRESS27
ADDRESS19ADDRESS20
ADDRESS22ADDRESS21
ADDRESS18
ADDRESS10
ADDRESS14
ADDRESS8ADDRESS9
ADDRESS12ADDRESS11
ADDRESS13
ADDRESS17ADDRESS16ADDRESS15
ADDRESS7
ADDRESS4ADDRESS3
ADDRESS6
ADDRESS2
ADDRESS5
ADDRESS1
ADDRESS0
CN
TL0
CN
TL1
CN
TL2
CN
TL3
CN
TL4
CN
TL5
CN
TL6
CN
TL7
CN
TL8
CN
TL9
CN
TL1
0C
NT
L11
CN
TL1
2C
NT
L13
CN
TL1
4
CN
TL1
5C
NT
L16
CN
TL1
7C
NT
L18
CN
TL1
9C
NT
L20
SWITCH9
SWITCH8SWITCH7SWITCH6SWITCH5SWITCH4SWITCH3SWITCH2
SWITCH1SWITCH0
LED
0LE
D1
LED
2LE
D3
LED
4LE
D5
LED
6LE
D7
CF_N
SWITCH[0:9]
JTAG_TMSJTAG_TDI
JTAG_TDOJTAG_TCK
JTAG_TRS
OSC
ADDRESS[0:31]
CNTL[0:20]
GCK3
CLK_OUT_FB
DATA[0:31]
RS232RXRS232TXRS232EN_NRS232SD_N
SEG2_C
SEG1_G
SEG2_G
SEG2_B
SEG1_E
SEG2_Dp
SEG2_A
SEG1_B
SEG1_Dp
SEG1_CSEG1_D
SEG2_E
SEG1_A
SEG2_D
SEG2_F
SEG1_F
TEMP_CE
TEMP_SDOTEMP_SDI
TEMP_SCLK
GCK1_FBGCK1
OSC_FB
DOUT
CLK_OUTIR_SHDN
IR_RXDIR_TXD
LED[0:7]
CLK_IN
VCCVCC
VCC
VCC
VCC
VCC
+1.8V3.3V
R15
Do Not Populate
1 2
U2
XC1801SO20
38
1011192018
1162
157
149
12
13
56417
CLKRST/OECE
GNDVCCO
VCCVCC
D0/DATAD1D2D3D4/CFD5D6D7
CEO
TMSTCKTDI
TDO
J2
Do Not Populate
1 2 3
A
Com
B
U1
VIRTEX E - PQ240
212213215216217218220221222223224226228229230231232234235236237238
180184185186187188189191192193194195197199200201202203205206207208209210
150
152
153
154
155
156
157
159
160
161
162
163
165
167
168
169
170
171
173
174
175
176
177
178
179
181
120
121
123
124
125
126
127
128
130
131
132
133
134
136
138
139
140
141
142
144
145
146
147
149
1001011021031051071081091101111131141151161171189092939495969799
6163646566676870717273747678798081828485868789
30 31 33 34 35 36 38 39 40 41 42 44 46 47 48 49 50 52 53 54 55 56 57 10 11 12 13 15 17 18 19 20 21 23 24 240
25 26 27 28 3 4 5 6 7 9 104
137
148
16164
198
214
225
32437788605862122
239
183
2
1106
112
119
129
135
14143
151
158
166
172
182
190
196
204
211
219
22227
233
293745515969758839198
VCCOGCK3
IO_LVDS_DLL_L6NIO_VREF
IO_L5P_YIO_VREF_L5N_Y
IO_L4P_YIO_L4N_Y
IOIO_L3P_YYIO_L3N_YY
VCCOIO_L2P_YY
IO_VREF_L2N_YYIO
IO_VREFVCCO
IO_L1P_YYIO_L1N_YY
IO_VREF_L0P_YIO_L0N_Y
IO
VCCOIO_CS_L14P_YY
IO_WRITE_L14N_YYIO_L13P
IO_VREF_L13NIO_L12P_YYIO_L12N_YY
IO_VREF_L11P_YYIO_L11N_YY
IOIO_VREF_L10P_YY
IO_L10N_YYVCCO
IO_L9P_YYIO_L9N_YY
IOIO_L8P_YIO_L8N_Y
IO_VREF_L7P_YIO_L7N_Y
VCCOIO_VREF
IO_LVDS_DLL_L6PGCK2
VC
CO
IO_L
23N
_YY
IO_L
23P
_YY
IO_V
RE
F_L
22N
IO_L
22P
IO_D
3_L2
1N_Y
IO_V
RE
F_L
21P
_YIO
_L20
N_Y
IO_L
20P
_YIOIO
_L19
N_Y
YIO
_D2_
L19P
_YY
VC
CO
IO_D
1_L1
8N_Y
IO_V
RE
F_L
18P
_YIOIO
_L17
N_Y
IO_V
RE
F_L
17P
_YIO
_L16
N_Y
IO_L
16P
_YIO
_VR
EF
VC
CO
IO_D
IN_D
0_L1
5N_Y
YIO
_DO
UT
_BU
SY
_L15
P_Y
YC
CLK
TD
O
DO
NE
VC
CO
IO_I
NIT
_L31
N_Y
YIO
_D7_
L31P
_YY
IO_L
30N
IO_V
RE
F_L
30P
IO_L
29N
_YIO
_L29
P_Y
IO_V
RE
F_L
28N
_YIO
_L28
P_Y
IOIO_V
RE
F_L
27N
_YIO
_D6_
L27P
_YV
CC
OIO
_D5_
L26N
_YY
IO_L
26P
_YY
IOIO_L
25N
_YIO
_L25
P_Y
IO_V
RE
F_L
24N
_YIO
_D4_
L24P
_YV
CC
OIO
_VR
EF
IO
IO_L37P_YIOIO_L36N_YYIO_L36P_YYVCCOIO_L35N_YYIO_VREF_L35P_YYIOIO_L34N_YYIO_VREF_L34P_YYIO_L33N_YYIO_L33P_YYIO_VREFVCCOIO_L32N_YYIO_L32P_YYVCCOGCK0IO_LVDS_DLL_L40PIO_VREF_L39NIO_L39PIO_L38N_YIO_VREF_L38P_YIO_L37N_Y
VCCOIO_L47N_YYIO_L47P_YYIO_L46N_YIO_VREF_L46P_YIO_L45N_YYIO_L45P_YYIO_VREF_L44N_YYIO_L44P_YYIOIO_VREF_L43N_YYIO_L43P_YYVCCOIO_L42N_YYIO_L42P_YYIOIOIO_L41NIO_VREF_L41PVCCOIO_VREFIO_LVDS_DLL_L40NGCK1 V
CC
O IOIO
_VR
EF
_L55
PIO
_L55
NIO
_L54
P_Y
IO_V
RE
F_L
54N
_YIO
_L53
P_Y
IO_L
53N
_Y IOIO
_L52
P_Y
YIO
_L52
N_Y
YV
CC
OIO
_L51
P_Y
IO_V
RE
F_L
51N
_Y IOIO
_L50
P_Y
IO_V
RE
F_L
50N
_YIO
_L49
P_Y
IO_L
49N
_YIO
_VR
EF
VC
CO
IO_L
48P
_YY
IO_L
48N
_YY
IO_L
61N
_Y IOIO
_VR
EF
_L60
P_Y
IO_L
60N
_YV
CC
OIO
_L59
P_Y
YIO
_L59
N_Y
Y IOIO
_L58
P_Y
IO_L
58N
_YIO
_VR
EF
_L57
P_Y
IO_L
57N
_YV
CC
OV
CC
OIO
_VR
EF
IO_L
56P
_YY
IO_L
56N
_YY IO
IO_L
63P
IO_V
RE
F_L
63N
IO_L
62P
_YIO
_L62
N_Y
IO_V
RE
F_L
61P
_Y
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
M0
M1
M2
PR
OG
RA
MT
CK
TD
IT
MS
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
D1
QTLP650C-4
R6
0R0/0805
1 2
R13
1K
12
R120R0/0805
12
JTAG1
JTAG Header
123456
J1
Do Not Populate
1 2 3
A
Com
B
R2
Do Not Populate
1 2
R110R0/0805
12
JP1
HEADER 2x1
12
R10Do Not Install
12
R7Do Not Install
12
R1
Do Not Populate
1 2
R9Do Not Install
12
R5
10K
1 2
JP2
HEADER 2x1
12
R4
10K
1 2
R3
10K
1 2
C1
0.1uF
12
R8Do Not Install
12
JP3
HEADER 2x1
12
R144.7K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AVNET, INC. CONFIDENTIAL
Virtex-E Decoupling Caps0.1 uf per Vccco47uf per Bank
Virtex-E Decoupling Caps0.1uf per Vccintfour 47uF per deviceone 470uF per device
3.3V1.8V
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Power
B
3Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
3.3V
+1.8V
5V
+1.8V
VCC
AUX+3.3V
3.3V
C7
0.1uF
12
+C37
TANC_47uF
12
R16
Do
Not
Pop
ulat
e12
C28
0.1uF
12
C16
0.1uF
12
C15
0.1uF
12
C38
0.1uF
12
C9
0.1uF
12
C39
0.1uF
12
C22
0.1uF1
2
C40
0.1uF
12
C13
0.1uF
12
+ C2
TANB_10uF
12
C41
0.1uF
12
+C46
TANC_47uF
12
C11
0.1uF
12
U4
TPS76718QPWP
35
67 13
14
1516
129
10 11121920
48
1817
GNDEN
ININ OUT
OUT
FBRST
GND/HSGND/HSGND/HSGND/HS GND/HS
GND/HSGND/HSGND/HS
NCNC
NCNC
C42
0.1uF
12
R18
Do
Not
Pop
ulat
e
12
C51
0.1uF
12
C43
0.1uF
12
C52
0.1uF
12
C44
0.1uF
12
C53
0.1uF
12
C45
0.1uF
12
C54
0.1uF
12
J3RAPC712
1
2
C19
0.1uF
12
C5
0.1uF
12
C18
0.1uF
12
C23
0.1uF
12
C10
0.1uF
12
+C47
TANC_47uF
12
R17
270K 10%
12
C29
0.1uF
12
+C48
TANC_47uF
12
+ C3
TANC_22uF
12
C8
0.1uF
12
C14
0.1uF
12
+C49
TANC_47uF
12
+ C4
TANC_22uF
12
+C30
TANC_47uF
12
C6
0.1uF
12
+C50
TAND_470uF
12
+C31
TANC_47uF
12
C27
0.1uF
12
JP4HEADER 3
1 2 3
U3 L4955V3.3
1
2
3
4
IN
GN
D
OUT
TA
B
+C32
TANC_47uF
12
C24
0.1uF
12
C20
0.1uF
12
+C33
TANC_47uF
12
C25
0.1uF
12
+C34
TANC_47uF
12
C21
0.1uF
12
+C35
TANC_47uF1
2
C17
0.1uF
12
C26
0.1uF
12
+C36
TANC_47uF
12
C12
0.1uF
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Connectors
B
4Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
ADDRESS18
ADDRESS12
ADDRESS8
ADDRESS0 ADDRESS1
ADDRESS30
ADDRESS20
ADDRESS28
ADDRESS16
ADDRESS3
ADDRESS9
ADDRESS4
ADDRESS26
ADDRESS16
ADDRESS7
ADDRESS22ADDRESS21
ADDRESS22
ADDRESS10 ADDRESS5
ADDRESS28ADDRESS27
ADDRESS7
ADDRESS1
ADDRESS13ADDRESS23
ADDRESS9
ADDRESS2
ADDRESS10
ADDRESS8
ADDRESS26
ADDRESS4
ADDRESS13
ADDRESS20ADDRESS11
ADDRESS19
ADDRESS11
ADDRESS24
ADDRESS5
ADDRESS15
ADDRESS12
ADDRESS17ADDRESS0
ADDRESS25
ADDRESS6
ADDRESS29
ADDRESS14
ADDRESS31
ADDRESS2
ADDRESS6
ADDRESS30ADDRESS14
ADDRESS18
ADDRESS3
ADDRESS24
DATA4
DATA13
DATA9DATA8
DATA3
DATA6DATA22
DATA11
DATA16
DATA31
DATA12DATA11
DATA5
DATA25
DATA0
DATA10
DATA7
DATA14
DATA18
DATA10
DATA20
DATA5
DATA22
DATA30
DATA0
DATA13
DATA2
DATA1
DATA14
DATA3
DATA9
DATA16
DATA17DATA2
DATA19
DATA24
DATA23DATA8
DATA30
DATA26
DATA6
DATA27
DATA15
DATA1
DATA28
DATA24
DATA29DATA18
DATA28
DATA12
DATA21
DATA7
DATA26
DATA20
DATA4
ADDRESS15ADDRESS17ADDRESS19ADDRESS21ADDRESS23ADDRESS25ADDRESS27ADDRESS29ADDRESS31
DATA15DATA17DATA19DATA21DATA23DATA25DATA27DATA29DATA31
CNTL14
CNTL2
CNTL16CNTL17
CNTL7
CNTL10
CNTL12
CNTL6
CNTL6
CNTL13
CNTL4
CNTL0
CNTL15
CNTL3
CNTL15
CNTL1
CNTL7
CNTL19CNTL17
CNTL5
CNTL0
CNTL3CNTL4
CNTL10
CNTL20
SWITCH9
CNTL1
CNTL19
SWITCH8
CNTL13
CNTL2
CNTL8CNTL9
CNTL11
CNTL5
CNTL11CNTL12
CNTL14
CNTL18
CNTL9
CNTL16
CNTL8
CNTL18
CNTL20
ADDRESS[0:31] ADDRESS[0:31]
OSCCLK_OUT
GCK3GCK1
DATA[0:31]
DATA[0:31]
CNTL[0:20]
CNTL[0:20]
CNTL[0:20]
CNTL[0:20]
SWITCH[0:9]
DOUT
TEMP_SCLK
RS232RX
CLK_OUT
TEMP_SDO
RS232TXRS232EN_N
TEMP_SDI
RS232SD_N
TEMP_CE
CLK_IN
CLK_OUTCLK_IN
OSC
CLK
_OU
T_F
B
GC
K1
GC
K3
DOUT
CNTL[0:20]
GCK1_FBOSC_FB
J5MICTOR(AMP 2-767004-2)
12345
67891011121314151617181920212223242526272829303132333435363738
3940414243
n/cn/cGNDn/c
CLK:0/Q0CLK:1/Q1
A/D3:7A/D1:7A/D3:6A/D1:6A/D3:5A/D1:5A/D3:4A/D1:4A/D3:3A/D1:3A/D3:2A/D1:2A/D3:1A/D1:1A/D3:0A/D1:0A/D2:7A/D0:7A/D2:6A/D0:6A/D2:5A/D0:5A/D2:4A/D0:4A/D2:3A/D0:3A/D2:2A/D0:2A/D2:1A/D0:1A/D2:0A/D0:0
GN
DG
ND
GN
DG
ND
GN
D
R190R0/0805
1 2
J4MICTOR(AMP 2-767004-2)
12345
67891011121314151617181920212223242526272829303132333435363738
3940414243
n/cn/cGNDn/c
CLK:0/Q0CLK:1/Q1
A/D3:7A/D1:7A/D3:6A/D1:6A/D3:5A/D1:5A/D3:4A/D1:4A/D3:3A/D1:3A/D3:2A/D1:2A/D3:1A/D1:1A/D3:0A/D1:0A/D2:7A/D0:7A/D2:6A/D0:6A/D2:5A/D0:5A/D2:4A/D0:4A/D2:3A/D0:3A/D2:2A/D0:2A/D2:1A/D0:1A/D2:0A/D0:0
GN
DG
ND
GN
DG
ND
GN
D
R210R0/0805
1 2
J6MICTOR(AMP 2-767004-2)
12345
67891011121314151617181920212223242526272829303132333435363738
3940414243
n/cn/cGNDn/c
CLK:0/Q0CLK:1/Q1
A/D3:7A/D1:7A/D3:6A/D1:6A/D3:5A/D1:5A/D3:4A/D1:4A/D3:3A/D1:3A/D3:2A/D1:2A/D3:1A/D1:1A/D3:0A/D1:0A/D2:7A/D0:7A/D2:6A/D0:6A/D2:5A/D0:5A/D2:4A/D0:4A/D2:3A/D0:3A/D2:2A/D0:2A/D2:1A/D0:1A/D2:0A/D0:0
GN
DG
ND
GN
DG
ND
GN
D
R220R0/0805
1 2
JP5
2-102977-5
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
R230R0/0805
12
R200R0/0805
12
JP6
2-102977-5
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
R25
0R0/0805
12
R260R0/0805
12 R24
0R0/0805
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Switch, LED, OSC
B
5Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
LED
0
LED
2
LED
3
LED
5
LED
6
LED
1
LED
4
LED
7
SWITCH2
SWITCH5
SWITCH8
SWITCH0
SWITCH1
SWITCH7
SWITCH3
SWITCH6
SWITCH4
SWITCH9
LED[0:7]
SWITCH[0:9]
OSC
RS232TX
RS232RX
RS232SD_N
RS232EN_N
TEMP_CE
TEMP_SDOTEMP_SDITEMP_SCLK
SEG1_F
SEG1_G
SEG1_A
SEG1_B
SEG1_E
SEG1_D
SEG1_C
SEG1_Dp
SEG2_E
SEG2_D
SEG2_G
SEG2_C
SEG2_Dp
SEG2_B
SEG2_F
SEG2_A
IR_TXD
IR_RXD
IR_SHDN
VCC
VCC
VCC
VCC
VCC
VCC
R2910K1 2
R49
0R0/0805
1 2
D9
QT
LP65
0C-2
+ C584.7uF, TAN
12
R2810K1 2
R2710K1 2
S1
3-435640-9
12345678
161514131211109
U7
MAN6141C
123456789
10 11121314151617181920E1
D1C1Dp1E2D2G2C2Dp2B2 A2
F2S2S1B1A1G1F1
N/C1N/C2
C55
0.1uF
12
C60
0.1uF
12
R34
1K
12
R3910K1 2
SW1
7914J-1-000E3
14
2
D6
QT
LP65
0C-2
R38
1K
12
R4310K1 2
R50
2201 2
R52
2201 2
OSC
U5
OSC/SOCKET
8
1
4
5
VCC
ENABLE
GND
OUT
C61
0.1uF
1 2
R4110K1 2
R54
2201 2
C62
0.1uF
1 2
R4410K1 2
R53
2201 2
R56
2201 2
R4510K1 2
R55
2201 2
R58
2201 2
U9
DS1722U
1234 5
678VDDD
CESCLKGND SDO
SDISERMODE
VDDA
R3010K1 2
R57
2201 2
R61
2201 2
R46
1206, 1.8R
12
D3
QT
LP65
0C-2
R35
1K
12
SW2
7914J-1-000E3
14
2
R59
2201 2
R64
2201 2
C56
0.1uF
12
R47
1206, 1.8R
12
R31
1K
12
R4810K1 2
R60
2201 2
R65
2201 2
C57
0.1uF
12
D7
QT
LP65
0C-2
R63
2201 2
R66
2201 2
R400R0/080512
U8
ADM3222ARS
123456789
10
20191817161514131211
ENC1+V+C1-C2+C2-V-T2OUTR2INR2OUT
SDVCCGND
T1OUTR1IN
R1OUTn/c
T1INT2IN
n/c
P1
747844-6
594837261
R32
1K
12
D2
QT
LP65
0C-2
R42
Do Not Populate
12
R51
2201 2
D4Q
TLP
650C
-2
R36
1K
12
U6
TFDU6101E
1
2
6
87
5
4
3 LEDA
LEDC
VCC
GNDMode
SHDN
RXD
TXD
D8
QT
LP65
0C-2
R67
DO NOT POPULATE
12
R62
0R0/0805
12
C59
0.1uF
1 2
C63
0.1uF
12
R33
1K
12
D5
QT
LP65
0C-2
R37
1K
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOT POPULATED
NOT POPULATED
NOT POPULATED
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Daughter Board Connector
B
6Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
ADDRESS15
ADDRESS9
ADDRESS1
ADDRESS8
ADDRESS21
ADDRESS28
ADDRESS4
ADDRESS23
ADDRESS20
ADDRESS24ADDRESS25
ADDRESS3
ADDRESS0
ADDRESS16
ADDRESS11
ADDRESS26
ADDRESS5
ADDRESS13
ADDRESS27
ADDRESS19
ADDRESS7
ADDRESS31
ADDRESS17
ADDRESS12
ADDRESS6
ADDRESS2
ADDRESS10
ADDRESS14
ADDRESS18
ADDRESS22
ADDRESS29ADDRESS30
DATA6
DATA22
DATA18
DATA9
DATA25
DATA10
DATA17
DATA21
DATA2DATA1
DATA30CNTL0
CNTL3CNTL4
CNTL7CNTL8
CNTL11CNTL12
CNTL15CNTL16
CNTL19CNTL20
CNTL1CNTL2
CNTL5CNTL6
CNTL9CNTL10
CNTL13CNTL14
CNTL17CNTL18
DATA15
DATA27
DATA4DATA5
DATA19
DATA12
DATA8DATA7
DATA28
DATA16
DATA24
DATA0
DATA11
DATA31
DATA3
DATA20
DATA13
DATA29
DATA14
DATA23
DATA26
ADDRESS[0:31]
DATA[0:31]
CNTL[0:20]CNTL[0:20]
CLK_OUTCLK_INCLK_OUT_FB
JTAG_TMS
JTAG_TDIJTAG_TRS
JTAG_TDOJTAG_TCK
DATA[0:31]
AUX+3.3V
R680R0/0805
12
R700R0/0805
12
P2
5-179010-6
1
4
23
56
89
7
101112131415
1718
2021
2324
16
19
22
252627
2930
3233
28
31
34353637
7172
75
78
7374
7677
7980
8283
8586
8889
9192
9495
9798
100101
103104
106107
81
84
87
93
96
99
105
90
102
108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140
3839404142434445464748
5051525354555657585960
626364656667686970
61
49
+5V
GND
IOIO
IOIO
IOIO
GND
GNDIOIO
+5VIOIO
IOIO
IOIO
IOIO
GND
GND
GND
+5VIOIO
IOIO
IOIO
GND
GND
GNDIOIO
+5V
IOGND
GND
+3.3V
IOIO
IOIO
IOIO
IOIO
IOIO
IOIO
IOIO
IOIO
IOIO
IOIO
IOIO
IOIO
GND
GND
GND
GND
GND
GND
GND
+3.3V
+3.3V
GNDIOIOGNDIOIO+3.3VIOIOGNDIOIOGNDIOIOGNDIOIO+3.3VIOIOGNDIOIOGNDIOIOGNDIOTMS+3.3VTDITRST
IOIO
GNDIOIO
GNDIOIO
GNDIOIO
IOIO
GNDIOIO
GNDIOIO
GNDIOIO
IOIO
GNDIOIO
GNDTDOTCKGND
+5V
+5V
R690R0/080512